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LT3686A 1 3686afa applic a tions 37v/1.2a step-down regulator in 3mm 3mm dfn and mse the lt ? 3686a is a current mode pwm step-down dc/dc converter with an internal power switch. the wide input range of 3.6v to 37v makes the LT3686A suitable for regulating power from a wide variety of sources, including 24v industrial supplies and automotive batteries. its high maximum frequency allows the use of tiny inductors and capacitors, resulting in a very small solution. operating frequency above the am band avoids interfering with radio reception, making the LT3686A particularly suitable for automotive applications. cycle-by-cycle current limit, thermal shutdown and da current sense provide protection against fault conditions. soft-start and frequency foldback eliminate input current surge during start-up. an optional internal regulated active load at the output via the bd pin keeps the LT3686A at full switching frequency at light loads, resulting in low, predictable output ripple above the audio and am bands. internal compensation and an internal boost diode reduce external component count. the LT3686A offers external synchronization capability, whereas the lt3686 does not. 3.3v step-down converter sw da fb sync/mode ss rt v in v in 6v to 37v bd v out 3.3v 1.2a 0.22f mbrm140 2.2f 2mhz 10nf 31.6k 22f 10k 6.8h 31.6k gnd LT3686A 3686a ta01a en/uvlo boost (v in 6v to 16v at 2mhz) 12v in effciency (2mhz) fe a tures description automotive systems battery-powered equipment wall transformer regulation distributed supply regulation wide input range: ope ration from 3.6v to 37v ove rvoltage lockout protects circuit through 60v transients low minimum on-time: conve rts 16v in to 3.3v out at 2mhz 1.2a output current adjustable frequency: 300khz to 2.5mhz constant switching frequency at light loads can be synchronized to external clock tracking and soft-start precision uvlo short-circuit robust i q in shutdown <1a internally compensated thermally enhanced msop and 3mm 3mm dfn pa ckages t ypic a l applic a tion l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. load current (ma) 0 0 efficiency (%) 10 30 40 50 70 400 800 1000 3686a ta01b 20 80 90 60 200 600 1200 5v out 3.3v out
LT3686A 2 3686afa p in con f i g ur a tion absolute m a xi m u m ra tin g s input voltage (v in ) (note 7) ...................................... 60v boost voltage ......................................................... 55v boost pin above sw pin ......................................... 25v fb voltage ................................................................... 6v en/uvlo voltage (note 7) ........................................ 60v bd voltage ................................................................ 25v rt voltage ...................................................................6v ss voltage ............................................................... 2.5v (note 1) or d er in f or ma tion lead free finish tape and reel part marking* package description temperature range LT3686Aedd#pbf LT3686Aedd#trpbf lfrk 10-lead plastic dfn C40c to 125c LT3686Aidd#pbf LT3686Aidd#trpbf lfrk 10-lead plastic dfn C40c to 125c LT3686Aemse#pbf LT3686Aemse#trpbf 3686a 12-lead plastic msop C40c to 125c LT3686Aimse#pbf LT3686Aimse#trpbf 3686a 12-lead plastic msop C40c to 125c LT3686Ahmse#pbf LT3686Ahmse#trpbf 3686a 12-lead plastic msop C40c to 150c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. *for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ top view 11 gnd dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 sw da boost sync/mode en/uvlo v in bd fb ss rt ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 6 gnd v in bd fb ss rt 12 11 10 9 8 7 sw sw da boost sync/mode en/uvlo top view 13 gnd mse package 12-lead plastic msop ja = 40c/w, jc = 10c/w exposed pad (pin 13) is gnd, must be soldered to pcb sync/mode voltage ................................................... 6v operating junction temperature range (note 2) LT3686Ae ........................................... C40c to 125c LT3686Ai............................................ C40c to 125c LT3686Ah .......................................... C40c to 150c storage temperature range ................... C65c to 150c lead temperature (mse package only, soldering, 10 sec) ................................................ 300c
LT3686A 3 3686afa parameter conditions min typ max units quiescent current at shutdown v en/uvlo < 0.4v v en/uvlo = 1v 0.1 10 1 15 a a quiescent current not switching, sync/mode 0.4v not switching, sync/mode 0.8v 1.1 1.2 1.3 1.4 ma ma internal undervoltage lockout 3.4 3.6 v overvoltage lockout 37 38 39 v feedback voltage v in = 3.6v ? 37v 0.790 0.785 0.8 0.8 0.810 0.815 v v fb pin bias current 60 100 na switching frequency i da < 1.2a r t = 15.4k, ida < 1.2a 0.3 1.9 2.1 2.5 2.3 mhz mhz minimum on time sync/mode > 0.8v, bd < 6v 100 110 ns minimum off time 150 200 ns switch v cesat i sw = 1.2a 680 mv switch current limit (note 3) 1.9 1.85 2.3 2.3 2.6 2.65 a a switch active current sw = 10v (note 4) sw = 0v (note 5) 400 20 600 30 a a boost pin current i sw = 1.2a 20 ma minimum boost voltage above switch i sw = 1.2a 2.2 2.4 v max bd pin active load current sync/mode > 0.8v, bd < 6v 30 40 ma bd pin voltage to disable active load 6 6.5 7 v da pin current to stop osc 1.2 1.7 a sync/mode high 0.8 v sync/mode low 0.4 v sync/mode bias current 0.2 a ss threshold 0.9 v ss source current v ss = 1v 1.3 2 2.7 a en/uvlo bias current v en/uvlo = 10v v en/uvlo = 0v 40 1 a a en/uvlo threshold to turn off 1.22 1.28 1.34 v en/uvlo hysteresis current 1.8 2.4 3 a boost diode forward drop i bd to i boost = 200ma 0.85 v the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 10v, v en/uvlo 1.34v. e lectric a l c h a r a cteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT3686Ae is guaranteed to meet performance specifcations from 0c to 125c junction temperature. specifcations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3686Ai is guaranteed over the full C40c to 125c operating junction temperature range. the LT3686Ah is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. (note 6) note 3: current limit guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycle. note 4: current fows into pin. note 5: current fows out of pin. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. see high temperature considerations section. also see operation section. note 7: absolute maximum voltage at v in and en/uvlo pins is 60v for nonrepetitive one second transients, and 55v for continuous operation.
LT3686A 4 3686afa 3.3v out effciency (2mhz) 5v out effciency v fb vs temperature overvoltage lockout (ovlo) 3.3v out maximum load current t a = 25c unless otherwise noted. switch voltage drop internal undervoltage lockout (uvlo) 5v out maximum load current load current (ma) 0 0 efficiency (%) 10 30 40 50 70 400 800 1000 3686a g01 20 80 90 60 200 600 1200 mode/sync < 0.4v mode/sync > 0.8v v in = 12v v out = 3.3v l = 6.8h f = 2mhz load current (ma) 0 0 efficiency (%) 10 30 40 50 70 400 800 1000 3686a g02 20 80 90 60 200 600 1200 mode/sync < 0.4v mode/sync > 0.8v v in = 12v v out = 5v l = 10h f = 2mhz v in (v) 0 0 i out (a) 0.2 0.6 0.8 1.0 1.2 1.6 3686a g03 0.4 1.8 2.0 1.4 20 30 10 40 v out = 3.3v l = 6.8h f = 2mhz minimum typical v in (v) 0 i out (a) 0.2 0.6 0.8 1.0 1.2 1.6 3686a g04 0.4 1.8 2.0 1.4 20 30 10 40 typical minimum v out = 5v l = 10h f = 2mhz i sw (ma) 0 0 v sw (mv) 100 300 400 500 600 800 3686a g05 200 900 700 1000 1500 500 2000 2500 150c 125c 25c ?50c temperature (c) ?50 0 2.0 v in (v) 2.5 3.5 4.0 3686a g06 3.0 100 150 50 temperature (c) ?50 0 35 v in (v) 36 38 40 39 3686a g07 37 100 150 50 temperature (c) ?50 0 780 v fb (mv) 790 810 820 3686a g08 800 100 150 50 t ypic a l p er f or ma nce c h a r a cteristics
LT3686A 5 3686afa switching frequency vs r t switching frequency vs temperature soft-start/track vs frequency (1mhz) soft-start/track vs v fb en/uvlo pin current switch current limit vs temperature current limit vs duty cycle t a = 25c unless otherwise noted. 3.3v out maximum v in for full frequency (2mhz) 5v out maximum v in for full frequency (2mhz) frequency (mhz) 0 0.5 0 r t (k) 50 250 200 300 3686a g09 100 150 1.5 2.52 1 temperature (c) ?50 0 1.90 frequency (mhz) 1.95 2.15 2.10 2.20 3686a g10 2.00 2.05 100 150 50 r t = 15.4k ss (mv) 5000 0 frequency (khz) 200 1000 800 1200 3686a g11 400 600 1500 2000 2500 1000 ss (mv) 2000 0 fb (mv) 100 800 700 900 3686a g12 200 300 400 500 600 600 800 1000 1200 400 en/uvlo (v) 100 0 en/uvlo (a) 5 40 35 45 3686a g13 10 15 20 25 30 30 40 50 20 temperature (c) 0 ?50 1.0 current limit (a) 3686a g14 1.5 2.0 2.5 3.0 50 100 150 duty cycle (%) 25 0 0 current limit (a) 3686a g15 0.5 1.0 1.5 2.5 2.0 3.0 50 75 100 da valley switch peak load current (ma) 500 0 0 v in (v) 3686a g16 5 10 15 25 20 1000 1500 mode/sync > 0.8 mode/sync < 0.4 v out = 3.3v l = 6.8h f = 2mhz load current (ma) 500 0 0 v in (v) 3686a g17 5 10 15 35 25 30 20 1000 mode/sync > 0.8 mode/sync < 0.4 v out = 5v l = 10h f = 2mhz t ypic a l p er f or ma nce c h a r a cteristics
LT3686A 6 3686afa continuous mode waveform t a = 25c unless otherwise noted. 3.3v out typical minimum input voltage 5v out typical minimum input voltage t ypic a l p er f or ma nce c h a r a cteristics light load discontinuous mode waveform fixed frequency no load waveform i load (ma) 1 0 v in (v) 1 2 3 4 5 6 7 10 100 1000 3686a g18 v out = 3.3v l = 15h f = 1mhz mode/sync > 0.8 mode/sync < 0.4 i load (ma) 1 0 v in (v) 1 2 4 5 6 3 8 7 10 100 1000 3686a g19 v out = 5v l = 22h f = 1mhz mode/sync > 0.8 mode/sync < 0.4 v in = 10v v out = 3.3v l = 6.8h f = 2mhz c out = 22f i load = 200ma mode/sync = 0v v sw 2v/div i l 200ma/div 200ns/div 3686a g20 v in = 10v v out = 3.3v l = 6.8h f = 2mhz c out = 22f i load = 0ma mode/sync = 3.3v v sw 2v/div i l 200ma/div 200ns/div 3686a g22 v in = 10v v out = 3.3v l = 6.8h f = 2mhz c out = 22f i load = 25ma mode/sync = 0v v sw 2v/div i l 200ma/div 200ns/div 3686a g21 v out = 5v l = 22h f = 1mhz i load = 5ma mode/sync = 0v 200ms/div 3686a g23 v in 1v/div v out 1v/div v out = 5v l = 22h f = 1mhz i load = 5ma mode/sync = 1v 200ms/div 3686a g24 v in 1v/div v out 1v/div v out = 5v l = 22h f = 1mhz i load = 500ma mode/sync = 0v 200ms/div 3686a g25 v in 1v/div v out 1v/div v out = 5v l = 22h f = 1mhz i load = 500ma mode/sync = 1v 200ms/div 3686a g26 v in 1v/div v out 1v/div start-up shutdown waveform i load = 5ma start-up shutdown waveform i load = 500ma start-up shutdown waveform i load = 500ma start-up shutdown waveform i load = 5ma
LT3686A 7 3686afa v in (pin 1/2): the v in pin supplies current to the LT3686As internal regulator and to the internal power switch. this pin must be locally bypassed. bd (pin 2/3): when the sync/mode pin is driven with clock pulses or tied greater than 0.8v, the LT3686A will prevent pulse-skipping at light loads by regulating an active load on the bd pin; see applications information section fixed frequency at light load. fb (pin 3/4): the LT3686A regulates its feedback pin to 0.8v. connect the feedback resistor divider tap to this pin. set the output voltage according to: r1 = r2 v out 0.8v ? 1 ? ? ? ? ? ? a good value for r2 is 10k. ss (pin 4/5): provides soft-start and tracking. an internal 2a current source tied to a 2.5v reference supplies cur - rent to this pin to charge an external capacitor to create a voltage ramp at the pin. feedback voltage and switching frequency both track ss voltage. feedback voltage stops tracking at 0.8v. ss is reset under uvlo, ovlo and thermal shutdown conditions. float the pin if soft-start feature is not being used. rt (pin 5/6): the rt pin is used to program the oscillator frequency. select the value of r t resistor according to table 1 in the applications section of the data sheet. p in fun c tions (dfn/mse) en/uvlo (pin 6/7): the en/uvlo pin is used to start up the LT3686A. pull the pin below 0.4v to shutdown the LT3686A. the 1.28v threshold can function as an accurate undervoltage lockout (uvlo), preventing the regulator from operating until the input voltage has reached the programmed level. do not drive the en/uvlo pin above v in . sync/mode (pin 7/8): the sync/mode pin is used to synchronize the internal oscillator of the LT3686A to an external signal. the sync signal can be driven by a signal with pulse width of at least 200ns on and off time. the sync/mode pin also acts as mode select for the bd active load; when it is driven with pulses or tied above 0.8v, the LT3686A will prevent pulse skipping at light loads by regulating an active load on the bd pin. to disable the active load, tie sync/mode to below 0.4v. boost (pin 8/9): the boost pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar npn power switch. da (pin 9/10): connect catch diode (d1) anode to this pin. sw (pin 10/11, 12): the sw pin is the output of the internal power switch. connect this pin to the inductor, catch diode and boost capacitor. gnd (exposed pad pin 11/pin 1, exposed pad pin 13): the exposed pad gnd pin is the only ground connection for the device. the exposed pad should be soldered to a large copper area to reduce thermal resistance.
LT3686A 8 3686afa osc int reg uvlo ovlo v in bd fb rt v c sync/mode frequency foldback slope comp active load boost r3 ss 0.8v v in 1.27v c2 c4 r1 r2 r4 r5 3686a bd en/ulvo onoff + + ? r s q q q1 c3 gnd da d1 c1 sw l1 v out driver gm b lock di ag r am
LT3686A 9 3686afa the LT3686A is a current mode step-down regulator. the en/uvlo pin is used to place the LT3686A in shut - down. the 1.28v threshold on the en/uvlo pin can be programmed by an external resistor divider (r4, r5) to disable the LT3686A. when the en/uvlo pin is driven above 1.28v, an internal regulator provides power to the control circuitry. this regulator includes both overvoltage and undervoltage lockout to prevent switching when v in is more than 37v or less than 3.6v. tracking soft-start is implemented by providing constant current via the ss pin to an external soft-start capacitor (c4) to generate a voltage ramp. fb voltage is regulated to the voltage at the ss pin until it exceeds 0.8v; fb is then regulated to the reference 0.8v. soft-start also reduces the oscillator frequency to avoid hitting current limit during start-up. the ss capacitor is reset during fault events such as overvoltage, undervoltage, thermal shutdown and startup. an oscillator is programmed by resistor r t . the oscillator sets an rs fip-fop, turning on the internal 1.2a power switch q1. an amplifer and comparator monitor the cur - rent fowing between the v in and sw pins, turning the switch off when this current reaches a level determined by the voltage at v c . an error amplifer measures the output voltage through an external resistor divider tied to the fb pin and servos the v c node. if the error amplifers output increases, more current is delivered to the output; if it decreases, less current is delivered. an active clamp (not shown) on the v c node provides current limit. the switch driver operates from either v in or from the boost pin. an external capacitor and the internal boost diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to fully saturate the internal bipolar npn power switch for effcient operation. a comparator monitors the current fowing through the catch diode via the da pin and reduces the LT3686As operating frequency when the da pin current exceeds the 1.7a valley current limit. this helps to control the output current in fault conditions such as shorted output with high input voltage. the da comparator works in conjunction with the switch peak current limit comparator to determine the maximum deliverable current of the LT3686A. the sync/mode pin doubles as mode select for the bd active load circuit. the active load is enabled when sync/mode is driven with sync pulses or tied above 0.8v and disabled when sync/mode is tied below 0.4v. the LT3686A will prevent pulse skipping at light loads by regulating the active load. the active load will assist startup by guaranteeing a minimum load to charge the boost capacitor. it also hastens the recharge of boost capacitor when operating beyond maximum duty cycle. the active load works only when the bd pin is less than 6v. o per a tion
LT3686A 10 3686afa input voltage range the input voltage range for the LT3686A applications depends on the output voltage and on the absolute maxi - mum ratings of the v in and boost pins. the minimum input voltage is determined by either the LT3686As minimum operating voltage of 3.6v, or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = v out + v d v in C v sw + v d where v d is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.67v at maximum load). this leads to a minimum input voltage of: v in(min) = v out + v d dc max C v d + v sw dc max can be adjusted with frequency. the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to sustain the charge across the boost capacitor. applic a tions i n f or ma tion fb resistor network the output voltage is programmed with a resistor divider between the output and the fb pin. choose the 1% resis - tors according to: r1 = r2 v out 0.8v ? 1 ? ? ? ? ? ? r2 should be 20k or less to avoid bias current errors. reference designators refer to the block diagram. programmable undervoltage lockout the en/uvlo pin can be programmed by an external re - sistor divider between v in and the en/uvlo pin. choose the resistors according to: r4 = r5 v in 1.28v ? 1 ? ? ? ? ? ? r4 also sets the hysteresis voltage for the programmable uvlo: hysteresis = r4 ? 2. 4a once v in drops below the programmed voltage, the LT3686A will enter a low quiescent current state (iq 15a). to shutdown the LT3686A completely (iq < 1a), reduce en/uvlo pin voltage to below 0.4v. figure 1. i q vs v en/uvlo (v in = 10v) figure 2. en/uvlo pin current en/uvlo (v) 1 10 i q (a) 1000 100 0 1 2 3 4 5 6 7 3686a f01 0.1 10000 8 en/uvlo (v) 5 10 en/uvlo (a) 20 25 30 35 40 15 0 10 20 30 40 50 3686a f02 0 45
LT3686A 11 3686afa applic a tions i n f or ma tion figure 3. continuous mode operation near minimum on time when the required on time decreases below the typical minimum on time of 100ns, instead of the switch pulse width becoming narrower to accommodate the lower duty cycle requirement, the switch pulse width remains fxed at 100ns. the inductor current ramps up to a value exceed - ing the load current and the output ripple increases. the part then remains off until the output voltage dips below the programmed value before it begins switching again (figure 4). figure 4. pulse skip occurs when required on time is below 100ns the maximum input voltage is determined by the absolute maximum ratings of the v in and boost pins. for fxed frequency operation, the maximum input voltage is de - termined by the minimum duty cycle dc min : v in(max) = v out + v d dc min C v d + v sw dc min can be adjusted with frequency. note that this is a restriction on the operating input voltage for fxed frequency operation; the circuit will tolerate transient inputs up to the absolute maximum ratings of the v in and boost pins. minimum on time as the input voltage is increased, the LT3686A is required to switch for shorter periods of time. delays associated with turning off the power switch dictate the minimum on time of the part. the minimum on time for the LT3686A is 100ns (figure 3). v in = 18v v out = 3.3v l = 6.8h c out = 22f i load = 1.2ma v out 100mv/div ac v sw 10v/div i l 500ma/div 500ns/div 3686a f03 v in = 35v v out = 3.3v l = 6.8h c out = 22f i out = 300ma v sw 20v/div i l 500ma/div v out 100ma/div ac 2s/div 3686a f04 provided that the load can tolerate the increased output voltage ripple and that the components have been prop - erly selected, operation while pulse skipping is safe and will not damage the part. as the input voltage increases, the inductor current ramps up quicker, the number of skipped pulses increases, and the output voltage ripple increases. inductor current may reach current limit when operating in pulse skip mode with small valued inductors. in this case, the LT3686A will periodically reduce its frequency
LT3686A 12 3686afa to keep the inductor valley current to 1.7a (figure 5). peak inductor current is therefore peak current plus minimum switch delay: 1.7a + (v in C v out )/l ? 100ns applic a tions i n f or ma tion table 1. r t vs frequency frequency (mhz) r t (k) min sync frequency (mhz) 2.5 9.53 n/a 2.3 12.1 n/a 2.1 15.4 n/a 1.9 20.0 n/a 1.8 22.6 2.50 1.7 25.5 2.30 1.5 31.6 1.99 1.3 40.2 1.70 1.1 52.3 1.42 0.9 69.8 1.14 0.7 97.6 0.874 0.5 150 0.615 0.3 280 0.363 frequency (mhz) 50 100 r t (k) 200 250 300 150 0 0.5 1 1.5 2 2.5 3686a f06a 0 frequency (mhz) 5 10 inductance (h) 20 25 40 30 35 15 0.25 0.75 5v out 1.25 1.75 2.25 3686a f06b 0 12v out 3.3v out figure 6a. switching frequency vs r t figure 6b. suggested inductance vs frequency figure 5. pulse skip with large load current will be limited by the da valley current limit. notice the flat inductor valley current and reduced switching frequency v in = 35v v out = 3.3v l = 6.8h c out = 22f i out = 1.2a v sw 10v/div i l 500ma/div v out 100ma/div ac 2s/div 3686a f05 the part is robust enough to survive prolonged opera - tion under these conditions as long as the peak inductor current does not exceed 2a. inductor current saturation and junction temperature may further limit performance during this operating regime. frequency selection the maximum frequency that the LT3686A can be pro - grammed to is 2.5mhz. the minimum frequency that the LT3686A can be programmed to is 300khz. the switching frequency is programmed by tying a 1% resistor from the rt pin to ground. table 1 can be used to select the value of r t . minimum on-time and edge loss must be taken into consideration when selecting the intended frequency of operation. higher switching frequency increases power dissipation and lowers effciency. finite transistor band - width limits the speed at which the power switch can be turned on and off, effectively setting the minimum on-time of the LT3686A. for a given output voltage, the minimum on-time determines the maximum input voltage to remain in continuous mode operation outlined in the minimum on time section of the data sheet. finite transition time results in a small amount of power dissipation each time the power switch turns on and off (edge loss). edge loss increases with frequency, switch current, and input voltage.
LT3686A 13 3686afa the sync/mode pin is used to synchronize the internal oscillator with an external square wave. the synchroniz - ing clock signal to the LT3686A should be below 2.5mhz with pulse width of at least 200ns on and off time, a low state below 0.4v and a high state above 0.8v. the sync frequency must be higher than the rt programmed fre - quency; see table 1. the inductor value should be chosen based on the rt frequency rather than the highest synchronization fre - quency. the sync/mode pin doubles as mode select for the bd active load circuit. the active load is enabled when sync/mode is driven with clock pulses or tied greater than 0.8v and disabled when sync/mode is tied below 0.4v. see fixed frequency at light load section. inductor selection and maximum output current a good frst choice for the inductor value is: l = 4(v out + v d ) f where v d is the voltage drop of the catch diode (~0.4v), l is in h, frequency is in mhz. with this value there will be no subharmonic oscillation. the inductors rms current rating must be greater than the maximum load current and its saturation current should be about 30% higher. for robust operation during fault conditions, the saturation current should be above 2a. to keep effciency high, the series resistance (dcr) should be less than 0.1. table 2 lists several vendors and types that are suitable. for small size, the inductor can be chosen according to: l = 2(v out + v d ) f applic a tions i n f or ma tion using a smaller value inductor will increase inductor current ripple and reduce the v in voltage at which the active load can keep the LT3686A at full switching frequency. there are several graphs in the typical performance characteristics section of this data sheet that show the maximum load current as a function of input voltage and inductor value for several popular output voltages. low inductance may result in discontinuous mode opera - tion, which is okay, but further reduces maximum load current. for details of the maximum output current and discontinuous mode operation, see linear technology application note 44. finally, for duty cycles greater than 50% (v out /v in > 0.5), there is a minimum inductance required to avoid subharmonic oscillations. see linear technology application note 19. catch diode a low capacitance 1-2a schottky diode is recommended for the catch diode, d1. the diode must have a reverse voltage rating equal to or greater than the maximum input voltage. the mbrm140 is a good choice; it is rated for 1a continuous forward current and a maximum reverse voltage of 40v. input capacitor bypass the input of the LT3686A circuit with a 2.2f or higher value ceramic capacitor of x7r or x5r type. y5v types have poor performance over temperature and ap - plied voltage and should not be used. a 2.2f ceramic is adequate to bypass the LT3686A and will easily handle the ripple current. however, if the input power source has high impedance, or there is signifcant inductance due to long wires or cables, additional bulk capacitance may be table 2. vendor url part series inductance rate(h) size (mm) sumida www.sumida.com cdrh4d28 cdrh5d28 cdrh8d28 1.2 to 4.7 2.5 to 10 2.5 to 33 4.5 x 4.5 5.5 x 5.5 8.3 x 8.3 toko www.toko.com a916cy d585lc 2 to 12 1.1 to 39 6.3 x 6.2 8.1 x 8 wrth elektronik www.we-online.com we-tpc(m) we-pd2(m) we-pd(s) 1 to 10 2.2 to 22 1 to 27 4.8 x 4.8 5.2 x 5.8 7. 3 x 7. 3
LT3686A 14 3686afa necessary. this can be provided with a low performance electrolytic capacitor. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capacitor is required to reduce the result - ing voltage ripple at the LT3686A and to force this very high frequency switching current into a tight local loop, minimizing emi. a 2.2f capacitor is capable of this task, but only if it is placed close to the LT3686A and the catch diode (see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maxi - mum input voltage rating of the LT3686A. a ceramic input capacitor combined with trace or cable inductance forms a high quality (underdamped) tank circuit. if the LT3686A circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3686As voltage rating. this situation is easily avoided; see the hot plugging safely section. output capacitor the output capacitor has two essential functions. along with the inductor, it flters the square wave generated by the LT3686A to produce the dc output. in this role it deter - mines the output ripple so low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the LT3686As control loop. ceramic capacitors have very low equivalent series resistance (esr) and provide the best ripple performance. a good value is: c out = 145 v out ? f where c out is in f and frequency is in mhz. use an x5r or x7r type and keep in mind that a ceramic capacitor biased with v out will have less than its nominal capacitance. this choice will provide low output ripple and good transient response. transient performance can be improved with a high value capacitor, but a phase lead capacitor across the feedback resistor, r1, may be required to get the full beneft (see the compensation section). for small size, the output capacitor can be chosen ac - cording to: c out = 83 v out ? f where c out is in f and frequency is in mhz. however, using an output capacitor this small results in an increased loop crossover frequency and increased sensitivity to noise, requiring careful pcb design. high performance electrolytic capacitors can be used for the output capacitor. low esr is important, so choose one that is intended for use in switching regulators. the esr should be specifed by the supplier and should be 0.1 or less. such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance, because the capacitor must be large to achieve low esr. table 3 lists several capacitor vendors. applic a tions i n f or ma tion table 3. vendor phone url part series comments panasonic (714) 373-7366 www.panasonic.com ceramic polymer tantalum eef series kemet (864) 963-6300 www.kemet.com ceramic tantalum t494, t495 sanyo (408) 794-9714 www.sanyovideo.com ceramic polymer tantalum poscap murata (404) 436-1300 www.murata.com ceramic avx www.avxcorp.com ceramic tantalum tps series taiyo yuden (864) 963-6300 www.taiyo-yuden.com ceramic
LT3686A 15 3686afa figure 7 shows the transient response of the LT3686A with several output capacitor choices. the output is 3.3v. the load current is stepped from 0.25a to 1a and back to 0.25a, and the oscilloscope traces show the output voltage. the upper photo shows the recommended value. the second photo shows the improved response (less voltage drop) resulting from a larger output capacitor and a phase lead capacitor. the last photo shows the response to a high performance electrolytic capacitor. transient performance is improved due to the large output capacitance. applic a tions i n f or ma tion boost and bd pin considerations capacitor c3 and the internal boost diode are used to generate a boost voltage that is higher than the input voltage. in most cases a 0.22f capacitor will work well. figure 8 shows two ways to arrange the boost circuit. the boost pin must be at least 2.2v above the sw pin for best effciency. for outputs of 3v and above, the standard circuit (figure 8a) is best. for outputs less than 3v and above 2.5v, place a discrete schottky diode (such as the figure 7. transient load response of the LT3686A with different output capacitors as the load current is stepped from 0.25a to 1a. v in = 12v, v out = 3.3v, l = 6.8h , frequency = 2mhz 32.4k 10k fb v out 22f 32.4k 10k fb v out 47pf 22f 2 32.4k 10k fb v out 100f sanyo 4tpb100m + 3686a f07a 3686a f07d 3686a f07g v out 50mv/div ac i l 500ma/div 20s/div 3686a f07b v out 50mv/div ac i l 500ma/div 20s/div 3686a f07c v out 50mv/div ac i l 500ma/div 20s/div 3686a f07e v out 50mv/div ac i l 500ma/div 20s/div 3686a f07h v out 50mv/div ac i l 500ma/div 20s/div 3686a f07i v out 50mv/div ac i l 500ma/div 20s/div 3686a f07f sync/mode < 0.4v sync/mode > 0.8v
LT3686A 16 3686afa applic a tions i n f or ma tion bat54) in parallel with the internal diode to reduce v d . the following equations can be used to calculate and minimize boost capacitance in f: c boost = 0.065 (v bd + v catch C v d ? 2.2) ? f v d is the forward drop of the boost diode, v catch is the forward drop of the catch diode (d1), and frequency is in mhz. a typical value of 0.22f can be used for c boost . for lower output voltages the bd pin can be tied to an external voltage source with adequate local bypassing (figure 8b). the above equations still apply for calculating the optimal boost capacitor for the chosen bd voltage. the absence of bd voltage during startup will increase minimum voltage to start and reduce effciency. you must also be sure that the maximum voltage rating of boost pin is not exceeded. the bd pin can also be tied to v in (figure 8c) but v in will be limited to 25v and the active load circuit is automatically disabled. the minimum operating voltage of an LT3686A applica - tion is limited by the undervoltage lockout (3.6v) and by the maximum duty cycle as outlined above. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or figure 8. sw da v in v in bd v out gnd v boost ? v sw ? v out max v boost ? v in + v out 8a 8b LT3686A boost sw da v in v in bd v out gnd v boost ? v sw ? v dd max v boost ? v in + v dd LT3686A boost v dd 8c sw da v in v in bd v out gnd v boost ? v sw ? v in max v boost ? 2v in LT3686A 3686a f08 boost
LT3686A 17 3686afa the LT3686A is turned on with its en/uvlo pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on the input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. figure 9 shows plots of minimum load to start and to run as a function of input voltage. in many cases applic a tions i n f or ma tion the discharged output capacitor will present a load to the switcher which will allow it to start. at light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. this reduces the minimum input voltage to approximately 400mv above v out . at higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle, requiring a higher input voltage to maintain regulation. as the LT3686A enters dropout, the boost capacitor voltage will be limited by v out , which is fxed by the maximum duty cycle. if the boost capacitors voltage during dropout falls figure 9a. typical minimum input voltage, v out = 3.3v, f = 1mhz, l = 15h, sync/mode < 0.4v i load (ma) 1 0 v in (v) 1 2 4 5 6 3 7 10 100 1000 3686a f09a start run sustain i load (ma) 1 0 v in (v) 1 2 4 5 6 7 8 3 9 10 100 1000 3686a f09b start run sustain i load (ma) 1 0 v in (v) 1 2 4 5 6 7 3 10 100 1000 3686a f09c run i load (ma) 1 0 v in (v) 1 2 4 5 7 6 8 3 10 100 1000 3686a f09d run figure 9b. typical minimum input voltage, v out = 5v, f = 1mhz, l = 22h, sync/mode < 0.4v figure 9c. typical minimum input voltage, v out = 3.3v, f = 1mhz, l = 15h, sync/mode > 0.8v figure 9d. typical minimum input voltage, v out = 5v, f = 1mhz, l = 22h, sync/mode > 0.8v
LT3686A 18 3686afa applic a tions i n f or ma tion below the minimum voltage to sustain boosted operation (2.2v across the boost capacitor), the output voltage will fall suddenly to: v out = (v in C2.2) ? dc max figure 9 shows the minimum v in necessary to sustain boosted operation during dropout. once v in drops below the sustain voltage, v in will need to reach the start voltage again to refresh the boost capacitor. the programmable undervoltage lockout (uvlo) function can be used to avoid operating unless v in is greater than the start voltage. fixed frequency at light load the LT3686A contains unique active load circuitry to allow for full frequency switching at very light loads. to enable the active load, drive the sync/mode pin with clock pulses or a dc voltage greater than 0.8v. typical fxed frequency nonsynchronous buck regulators skip pulses at light loads. with a fxed input voltage, as the load current decreases in discontinuous mode, the regula - tor is required to switch for shorter periods of time. when the required on time decreases below the typical minimum on time, the regulator skips one or more pulses so the effective average duty cycle is equal to the required duty cycle. this likelihood of entering pulse-skipping is exacer - bated by the tendency for minimum on time to increase at very light loads. pulse-skipping is undesirable because it causes unpredictable, sub-harmonic output ripple that can interfere with the operation of other sensitive components such as am receivers and audio equipment. the bd active load is designed to combat pulse-skipping by providing an operational regime between full frequency discontinuous and pulse-skipping modes. the maximum v in before pulse-skipping in discontinu - ous mode is directly dependent on load current; as the load decreases, so does the pulse-skipping boundary. an artifcial load on the output helps push the pulse-skipping boundary higher. the LT3686A achieves this goal by commanding the minimum load necessary to keep itself at full switching frequency, hence the circuitry is called an active load. as the LT3686A approaches minimum on time in dis - continuous mode, its power switch transitions smoothly into a fxed on time, fxed frequency, open loop current source. instead of controlling switch current, the internal error amplifer servos the active load on the output via the bd pin to maintain output voltage regulation. the impact on effciency is mitigated by pulling the minimum current necessary to keep switching at full frequency. the necessary bd load to maintain output regulation depends on v in , inductor size, and load current. as the necessary bd load increases beyond its 40ma limit, pulse-skipping mode will resume. the bd active load circuitry is enabled when mode tied high and disabled when mode is tied low. even when activated, the active load will shutdown when bd voltage exceeds either 6v or v in in an effort to minimize power dissipation and intelligently react to external confgurations. to address the startup concerns delineated in the boost and bd pin considerations section, the active load will assist startup by pulling maximum current (40ma) to charge the boost capacitor voltage in the absence of an adequate load. an internal power good circuit will disable the bd active load when v fb reaches 0.7v. figure 9 com - pares plots of minimum input voltage to start and run as a function of load current. in many cases the discharged output capacitor will present a load to the switcher which will allow it to start. the plots show the worst-case situ - ation where v in is ramping very slowly. the active load also activates to hasten the recharge of boost cap when operating beyond maximum duty cycle. when not in use, the active load pulls no current. figure 10. regions of operation (5v out , 2mhz) i out (ma) 0 0 v in (v) 5 10 20 25 35 30 40 15 20 40 60 100 120 140 80 3686a f10 ccm dcm active load pulse-skipping
LT3686A 19 3686afa applic a tions i n f or ma tion soft-start the ss pin is used to soft-start the LT3686A, eliminating input current surge during start-up. it can also be used to track another voltage in the system (figure 11). an internal 2a current source charges an external soft- start capacitor to generate a voltage ramp. fb voltage is figure 12. to soft start the LT3686A, add a capacitor to the ss pin figure 11. LT3686A confgured to track voltage on ss pin v ss 500mv/div v out 2v/div 1ms/div 3686a f11 v sw 10v/div v out 2v/div i l 500ma/div 5s/div v in = 10v v out = 3.3v l = 6.8h c out = 22f c ss = 0 ss gnd ss 1.2nf gnd v sw 10v/div v out 2v/div i l 500ma/div 50s/div 3686a f12 v in = 10v v out = 3.3v l = 6.8h c out = 22f c ss = 1.2nf regulated to the voltage at the ss pin until it exceeds 0.8v, fb is then regulated to the reference 0.8v. soft-start also reduces the oscillator frequency to avoid hitting current limit during start-up. figure 12 shows the start-up wave - forms with and without the soft-start circuit.
LT3686A 20 3686afa applic a tions i n f or ma tion short and reverse protection if the inductor is chosen so that it wont saturate excessively, the LT3686A will tolerate a shorted output. when operat - ing in short-circuit condition, the LT3686A will reduce its frequency until the valley current is 1.7a (figure 13). there is another situation to consider in systems where the output will be held high when the input to the LT3686A is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode or-ed with the LT3686As output. if the v in pin is allowed to foat and the en/uvlo pin is held high (either by a logic signal or because it is tied to v in ), then the LT3686As internal circuitry will pull its quiescent current through its sw pin. this is fne if your system can tolerate a few ma in this state. if you ground the en/uvlo pin, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the LT3686A can pull large currents from the output through the sw pin and the v in pin. figure 14 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. hot plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of LT3686A circuits. however, these capacitors can cause problems if the LT3686A is plugged into a live supply (see linear technology application note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the v in pin of the LT3686A can ring to twice the nominal input voltage, possibly exceeding the LT3686As rating and damaging the part. if the input supply is poorly controlled or the user will be plugging figure 13. the LT3686A reduces its frequency from 2mhz to 160khz to protect against shorted output figure 14. input diode prevents a shorted input from discharging a backup battery tied to the output; it also protects the circuit from a reversed input. the LT3686A runs only when the input is present sw da fb sync/mode ss rt v in v in bd v out gnd LT3686A 3686a f14 en/uvlo boost v sw 20v/div i l 500ma/div 2s/div 3686a f13 v in = 35v l = 6.8h c out = 22f r t = 17.4k v out = 0v
LT3686A 21 3686afa applic a tions i n f or ma tion the LT3686A into an energized supply, the input network should be designed to prevent this overshoot. figure 15 shows the waveforms that result when an LT3686A circuit is connected to a 24v supply through six feet of 24-gauge twisted pair. the frst plot is the response with a 2.2f ceramic capacitor at the input. the input voltage rings as high as 35v and the input current peaks at 20a. one method of damping the tank circuit is to add another capacitor with a series resistor to the circuit. in figure 15b an aluminum electrolytic capacitor has been added. this capacitors high equivalent series resistance damps the circuit and eliminates the voltage overshoot. the extra capacitor improves low frequency ripple fltering and can slightly improve the effciency of the circuit, though it is likely to be the largest component in the circuit. an alternative solution is shown in figure 15c. a 1 resistor is added in series with the input to eliminate the voltage overshoot (it also reduces the peak input current). a 0.1f capacitor improves high frequency fltering. this solution is smaller and less expensive than the electrolytic capacitor. for high input voltages its impact on effciency is minor, reducing effciency one percent for a 5v output at full load operating from 24v. figure 15. a well chosen input network prevents input voltage overshoot and ensures reliable operation when the LT3686A is connected to a live supply + + LT3686A 2.2f v in 20v/div i in 5a/div 20s/div v in closing switch simulates hot plug i in (15a) (15b) (15c) low impedance energized 24v supply stray inductance due to 6 feet (2 meters) of twisted pair + + LT3686A 2.2f 10f 35v ai.ei. LT3686A 2.2f 0.1f 1 3686a f15 v in 20v/div i in 5a/div 20s/div v in 20v/div i in 5a/div 20s/div danger! ringing v in may exceed absolute maximum rating of the LT3686A
LT3686A 22 3686afa applic a tions i n f or ma tion figure 16. model for loop response frequency compensation the LT3686A uses current mode control to regulate the output. this simplifes loop compensation. in particular, the LT3686A does not require the esr of the output ca - pacitor for stability allowing the use of ceramic capacitors to achieve low output ripple and small circuit size. figure 16 shows an equivalent circuit for the LT3686A control loop. the error amp is a transconductance amplifer with fnite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifer generating an output cur - rent proportional to the voltage at the v c node. note that the output capacitor integrates this current, and that the capacitor on the v c node (c c ) integrates the error ampli - fer output current, resulting in two poles in the loop. r c provides a zero. with the recommended output capacitor, the loop crossover occurs above the r c c c zero. this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. with a larger ceramic capacitor (very low esr), crossover may be lower and a phase lead capacitor (cpl) across the feedback divider may improve the phase margin and transient response. large electrolytic capacitors may have an esr large enough to create an additional zero, and the phase lead may not be necessary. if the output capacitor is different than the rec - ommended capacitor, stability should be checked across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. 800mv fb r1 c pl r2 error amplifier current mode power stage gnd LT3686A 1v 1m r c 160k v c c c 100pf ? + ? + g m = 200a/v g m = 2a/v esr 3686a f16 out c1 c1 +
LT3686A 23 3686afa figure 17. pcb layout pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 17 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents fow in the LT3686As v in and sw pins, the catch diode (d1) and the input capacitor (c2). the loop formed by these components should be as small as possible and tied to system ground in only one place. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board, and their connections should be made on that layer. place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor c1. the sw and boost nodes should be as small as possible. finally, keep the fb node small so that the ground pin and ground traces will shield it from the sw and boost nodes. include vias near the exposed gnd pad of the LT3686A to help remove heat from the LT3686A to the ground plane. high temperature considerations the die temperature of the LT3686A must be lower than the maximum rating of 125c (150c for LT3686Ah). for high ambient temperatures, care should be taken in the layout of the circuit to ensure good heat sinking of the LT3686A. the maximum load current should be derated as the ambient temperature approaches the maximum allowed junction temperature. the die temperature is calculated by multiplying the LT3686A power dissipa - tion by the thermal resistance from junction to ambient. power dissipation within the LT3686A can be estimated by calculating the total power loss from an effciency measurement and subtracting the catch diode loss. the resulting temperature rise at full load is nearly independent of input voltage. thermal resistance depends on the layout of the circuit board, but 43c/w is typical for the (3mm 3mm) dfn package. applic a tions i n f or ma tion 3686a f17 rt uvlo da bst bd out sw d1 v in sync/ mode ss fb c2 c1
LT3686A 24 3686afa sw da fb sync/mode ss rt v in v in 30v to 36v 2.2 100n 61.9k 10k 301k 100h 0.22f 0.22f 10f 15v bd v out 500ma gnd LT3686A 3686a f18 en/uvlo boost figure 18. 25v step-down converter outputs greater than 19v note that for outputs above 19v, the input voltage range will be limited by the maximum rating of the boost pin. the sum of input and output voltages cannot exceed the boost pins 55v rating. the 25v circuit (figure 18) shows how to overcome this limitation using an additional zener diode. other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note 318 shows how to generate a bipolar output supply using a buck regulator. applic a tions i n f or ma tion
LT3686A 25 3686afa t ypic a l applic a tions 0.8v step-down converter 3.3v step-down converter 1.8v step-down converter sw da fb sync/mode ss rt v in v in 3.6v to 25v bd v out 0.8v 1.2a 0.22f 2.2f 1nf 100f 3686a ta02a 61.9k 2.2h gnd LT3686A en/uvlo boost sw da fb sync/mode ss rt v in v in 5v to 37v bd v out 3.3v 1.2a 0.22f 2.2f 1nf 22f 10k 61.9k 6.8h 31.6k gnd LT3686A en/uvlo boost 3686a ta02b sw da fb sync/mode ss rt v in v in 3.6v to 25v bd v out 1.8v 1.2a 0.22f 2.2f 1nf 47f 10k 61.9k 3.3h 12.4k gnd LT3686A en/uvlo boost 3686a ta02c
LT3686A 26 3686afa t ypic a l applic a tions 2.5v step-down converter 5v step-down converter 3.3v step-down converter with programmed uvlo sw da fb sync/mode ss rt v in v in 7.5v to 37v bd v out 3.3v 1.2a 0.22f 2.2f 500k 100k 1nf 22f 10k 61.9k 6.8h 31.6k gnd LT3686A en/uvlo boost 3686a ta02d sw da fb sync/mode ss rt v in v in 3.6v to 25v bd v out 2.5v 1.2a 0.22f 2.2f 1nf 33f 10k 61.9k 4.7h 21.5k gnd LT3686A en/uvlo boost 3686a ta02e sw da fb sync/mode ss rt v in v in 7v to 37v bd v out 5v 1.2a 0.22f 2.2f 1nf 15f 10k 61.9k 10h 52.3k gnd LT3686A 3686a ta02f en/uvlo boost
LT3686A 27 3686afa pa ck ag e description mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev d) msop (mse12) 0910 rev d 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
LT3686A 28 3686afa pa ck ag e description 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c)
LT3686A 29 3686afa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h istory rev date description page number a 5/11 revised msop in features, pin confguration, order information and package description sections updated electrical characteristics section updated value for en/uvlo pin in pin functions section updated values in operation section revised equation in programmable undervoltage lockout section, table 1 and minor text edit to minimum on time in applications information section 1, 2, 27 3 7 9 10, 12, 13
LT3686A 30 3686afa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0511 rev a ? printed in usa part number description comments lt3686 37v, 55v with transient protection 1.2a, 2.5mhz, high effciency step-down dc/dc converter v in : 3.6v to 37v, transient to 55v, v out(min) = 0.8v, i q = 1.1ma, i sd <1a, 10-pin 3mm 3mm dfn package lt3689 36v, 60v transient protection, 800ma, 2.2mhz, high effciency micropower step-down dc/dc converter with por reset and watchdog timer v in : 3.6v to 36v transient to 60v, v out(min) = 0.8v, i q = 75a, i sd <1a, 16-pin 3mm 3mm qfn package lt3682 36v, 60v max , 1a, 2.2mhz, high effciency micropower step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 75a, i sd <1a, 12-pin 3mm 3mm dfn package lt3970 40v, 350ma (i out ), 2.2mhz, high effciency step-down dc/dc converter with only 2.5a of quiescent current v in : 4.2v to 40v, v out(min) = 1.21v, i q = 2.5a, i sd <1a, 10-pin 2mm 3mm dfn, 10-pin msop packages lt3990 60v, 350ma (i out ), 2.2mhz, high effciency step-down dc/dc converter with only 2.5a of quiescent current v in : 4.2v to 60v, v out(min) = 1.21v, i q = 2.5a, i sd <1a, 10-pin 3mm 3mm dfn, 16-pin msope packages lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high effciency step-down dc/dc converter with burst mode ? operation v in : 3.6v to 38v, v out(min) = 0.78v, i q = 70a, i sd <1a, 10-pin 3mm 3mm dfn, 10-pin msop packages lt3685 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high effciency step-down dc/dc converter v in : 3.6v to 38v, v out(min) = 0.78v, i q = 70a, i sd <1a, 10-pin 3mm 3mm dfn, 10-pin msop packages lt3505 36v with transient protection to 40v, 1.4a (i out ), 3mhz, high effciency step-down dc/dc converter v in : 3.6v to 34v, v out(min) = 0.78v, i q = 2ma, i sd = 2a, 8-pin 3mm 3mm dfn, 8-pin msop packages lt3437 60v, 400ma (i out ), micropower step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out(min) = 1.25v, i q = 100a, i sd <1a, 10-pin 3mm 3mm dfn, 16-pin tssop packages lt1976/lt1977 60v, 1.2a (i out ), 200/500khz, high effciency step-down dc/dc converter with burst mode operation v in : 3.3v to 60v, v out(min) = 1.2v, i q = 100a, i sd <1a, 16-pin tssop package rel a te d pa rts t ypic a l applic a tion 5v step-down converter sw da fb sync/mode ss rt v in v in 7v to 37v bd v out 5v 1.2a 0.22f 2.2f 1nf 15f 10k 61.9k 10h 52.3k gnd LT3686A 3686a ta02f en/uvlo boost

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